The present invention relates to a semiconductor device comprising a switch such as a redundancy circuit for relieving a random access memory (RAM) of its failures.
FIG. 47 is a circuit diagram of a conventional semiconductor device. The conventional semiconductor device comprises a 5-bit word mode RAM 100, a scan path circuit 210a, a failure relief circuit 220a, and a logic circuit 300. The RAM 100 and the logic circuit 300 exchange data therebetween through the failure relief circuit 220a. A detailed description of the scan path circuit 210a and the failure relief circuit 220a is given for example in Japanese Patent Laid-open No. P08-94718A.
The scan path circuit 210a receives and holds 5-bit data transmitted over lines L1 through L5, rewrites 5-bit data therein on the basis of serial data SS1 from a line L19, and outputs 5-bit data therein as serial data SS2 to a line L20. The scan path circuit 210a also outputs 4 bits of 5-bit data therein in parallel form as 1-bit data G1 through G4.
Whether or not there is an error in the data transmitted over the lines L1 through L5 can be checked by looking up the serial data SS2 from the scan path circuit 210a, so the RAM 100 can be tested for failure.
The scan path circuit 210a and the failure relief circuit 220a serve as a redundancy circuit for relieving the RAM 100 of its failures. For example, if there is an error in the third bit of the RAM 100, the serial data SS1 on the line L19 is set properly so that the 1-bit data G1 through G4 are set to xe2x80x9c1xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, respectively. This provides connections between the lines L11 and L1, between the lines L12 and L2, between the lines L13 and L4, and between the lines L14 and L5, except the line L3 of trouble. Similarly, connections are made between lines L15 and L6, between a line L16 and lines L7, L8, between lines L17 and L9, and between lines L18 and L10. Thus, even if the RAM 100 contains such a failure bit, it can be used as a trouble-free 4-bit word mode RAM, when viewed from the logic circuit 300, by making connections between the lines L1 through L10, except a trouble line, and the lines L11 through L18.
However, since the lines L11 through L14 are connected to four lines selected from among the five lines L1 through L5 according to data on the lines L1 through L5 and on the line L19, and since the data on the lines L1 through L5 may not be correct due to a failure in the RAM 100, it would be considerably difficult for the failure relief circuit 220a to determine which of the lines L11 through L14 each data on the lines L1 through L5 is transmitted to.
The above problem offers a considerable difficulty in testing the logic circuit 300. For example, a predetermined expected value is stored into the RAM 100 at every address and applied to the logic circuit 300 through the failure relief circuit 220a. This enables the test of whether the logic circuit 300 operates as intended or not. In such a test, which of the lines L11 through L14 each expected value on the lines L1 through L5 is transmitted to has to be determined from the expected value itself. However, if a failure occurs in the RAM 100, this determination becomes hard to be made, and thus, a serious difficulty arises in the test of the logic circuit 300.
A first aspect of the present invention is directed to a semiconductor device comprising: a memory circuit outputting N-bit data (Nxe2x89xa72) in parallel form; a switch including a data holding circuit having a scan path circuit receiving and holding the N-bit data from the memory circuit, the switch receiving a switch control signal and selecting and outputting M-bit data (M less than N) from the N-bit data of the memory circuit, the M-bit data outputted from the switch being predetermined M-bit data out of the N-bit data from the memory circuit if the switch control signal satisfies a predetermined condition, and being M-bit data determined according to data held in the data holding circuit if the switch control signal does not satisfy the predetermined condition; and a logic circuit to be tested, receiving the M-bit data outputted from the switch.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, the switch selects and outputs M-bit data directly outputted from the memory circuit.
According to a third aspect of the present invention, in the semiconductor device of the first aspect, the switch selects and outputs M-bit data in the scan path circuit from the memory circuit.
According to a fourth aspect of the present invention, in the semiconductor device of the first aspect, the switch further includes a selector block for selecting and outputting M-bit data from the memory circuit if the switch control signal satisfies the predetermined condition and for selecting and outputting M-bit data from the scan path circuit if the switch control signal does not satisfy the predetermined condition.
According to a fifth aspect of the present invention, in the semiconductor device of the first aspect, the data holding circuit further includes a register for holding data outputted from the scan path circuit.
According to a sixth aspect of the present invention, in the semiconductor device of the fifth aspect, if the switch control signal satisfies the predetermined condition, the register resets data held therein with a predetermined value.
According to a seventh aspect of the present invention, in the semiconductor device of the first aspect, the scan path circuit includes a plurality of series-connected scan path blocks, each of the plurality of scan path blocks having a comparator and receiving 1-bit data from expected data and resetting data held therein with a predetermined value according to a comparison result between the 1-bit data from the expected data and the 1-bit data from the memory circuit.
According to an eighth aspect of the present invention, in the semiconductor device of the first aspect, each of the plurality of scan path blocks resets data held therein with another predetermined value, if the switch control signal satisfies the predetermined condition.
According to a ninth aspect of the present invention, in the semiconductor device of the seventh aspect, each of the plurality of scan path blocks includes a selector for selecting either 1-bit data held therein or serial data from an ante-stage scan path block and for outputting the selected data to a post-stage scan path block.
According to a tenth aspect of the present invention, in the semiconductor device of the seventh aspect, the data holding circuit further includes a register for holding data outputted from the scan path circuit; each of the plurality of scan path blocks changes the comparison result into a predetermined value according to 1-bit data from the register.
In accordance with the first aspect, if the switch control signal satisfies a predetermined condition, the switch selects and outputs predetermined M-bit data out of the N-bit data from the memory circuit. This eliminates the need for determining a signal transmission path to which the data is transmitted according to the data held in the data holding circuit, thus facilitating a test of the logic circuit using the scan path circuit and the memory circuit.
In accordance with the second aspect, the logic circuit can be tested using the M-bit data outputted from the memory circuit.
In accordance with the third aspect, the logic circuit can be tested using the data outputted from the scan path circuit.
In accordance with the fourth aspect, the switch can be composed of the data holding circuit and the selector blocks.
In accordance with the fifth aspect, if the switch control signal does not satisfy a predetermined condition, the switch selects and outputs data corresponding to the data held in the register independently of the data held in the scan path circuit.
In accordance with the sixth aspect, the operation of the switch can be achieved through the use of the register.
In accordance with the seventh aspect, a failure in the memory circuit can be detected.
In accordance with the eighth aspect, the operation of the switch can be achieved through the use of the scan path circuit.
In accordance with the ninth aspect, it is possible to determine whether or not the memory circuit can be relieved of its failures.
In accordance with the tenth aspect, it is possible to determine whether or not the memory circuit can be relieved of its failures.
An object of the present invention is to provide a semiconductor device that can solve the aforementioned conventional problem and has no need for determining a signal transmission path to which data is transmitted according to the data.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.